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# VLSI Interview questions - Intel

- 5-19-2009
- Categorized in: VLSI

**Paper 1**

** **

1. Find Voltage across R and C in the following circuits.

a. In a given RC circuit find the voltage across C and R?

b. In a given CR circuit find the voltage across R and C ?;

2. For the given _expression Y=A’B’C+A’BC+AB’C+ABC+ABC’ realize using the following

a. 2 input and 3input NAND gate

b. 2 input and 3 input NOR gate

c. AND,OR, INVERTER.

d. INVERTER;

3. What is the importance of scan in digital system.;

4.Given A XOR B =C, such that prove the following

a. B XOR C =A

b. A XOR BXOR C=0;

5. Construct an input test pattern that can detect the result E stuck at 1 in the ckt below

NAND (A,B)->E, NAND(C,D)->F

AND(E,F)->A.

6. In a given opamp ckt input offcet is 5mv,volatage gain =10,000,vsat=+-15v

such that find the output voltage .

7. Draw the p side equation of the circuit.(I am not sulre about it)

8. Make a JK FF using a D FF and 4->1 MUX.

9.Use 2->1 MUX to implement the following _expression

Y=A+BC’+BC(A+B).

10.For the following ckt what is the relation between fin and fout.?

the D FF use +ve edge triggered and have a intial value is 0

CLK->two DFFs with complementing (i.e one DFF have CLK and other one have

Complement of it),inputs of DFF is same and output of DFFs is given to NOR

Gate and output of NOR gate is feedback to the two DFFs.

11. Design a asyncronous circuit for the following clk waveforms.

CLK->thrice the CLK period->half the period of input.

12. What is the setup time and hold time parameters of the FF, what happens if we are not

consider it in designing the digital ckt.

13. Given two DFF A,B ones output is the input of other and have the common clock.

Fmax if A and B are +ve edge triggered, if A is+ve edge triggered ,B is -ve edge triggered what is the Fmax relation to previous Fmax relation…

14. What are the FIFOS .? give some use of FIFOS in design.

**Paper II**

1. What is FIFO ? where it is used?

2. what is set-up and hold time?

3. Two +ive triggered FFs are connected in series and if the maximum frequency that can

operate this circuit is Fmax. Now assume other circuit that has +ive trigger FF followed by –ive trigger FF than what would be maximum frequency in terms of the Fmax that the circuit can work?

4. layout of gates were shown and u have to identify the gates (NAND & NOR gates)

5. make a JK FF using a mux(4:1) and a FF.

6. the waveform of clk, i/p and o/p were shown and u have to make a seqential circuit that

should satisfy the required waveform.

7. resistor is connected in series with capacitor and the input is dc voltage. Draw the waveform across the capacitor and resistor.

8. two FFs, one is –ive triggered and other is +ive triggered are connected in parallel. The 2 i/p NAND gate is has the i/ps from the q_out of both the FFs and the output of the NAND gate is connected with the I/p of both FFs . Find the frequency of the output of the NAND gate w.r.t clk.

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